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| IDT79R3051/79R3052 RISControllersTM Integrated Device Technology, Inc. IDT79R3051TM , 79R3051E IDT79R3052TM , 79R3052E FEATURES: * Instruction set compatible with IDT79R3000A and IDT79R3001 MIPS RISC CPUs * High level of integration minimizes system cost, power consumption -- IDT79R3000A /IDT79R3001 RISC Integer CPU -- R3051 features 4KB of Instruction Cache -- R3052 features 8KB of Instruction Cache -- All devices feature 2kB of Data Cache -- "E" Versions (Extended Architecture) feature full function Memory Management Unit, including 64entry Translation Lookaside Buffer (TLB) -- 4-deep write buffer eliminates memory write stalls -- 4-deep read buffer supports burst refill from slow memory devices * * * * * * -- On-chip DMA arbiter -- Bus Interface minimizes design complexity Single clock input with 40%-60% duty cycle 35 MIPS, over 64,000 Dhrystones at 40MHz Low-cost 84-pin PLCC packaging that's pin-/packagecompatible with thermally enhanced 84-pin MQUAD. Flexible bus interface allows simple, low-cost designs 20, 25, 33, and 40MHz operation Complete software support -- Optimizing compilers -- Real-time operating systems -- Monitors/debuggers -- Floating Point Software -- Page Description Languages Clk2xIn Clock Generator Unit Master Pipeline Control System Control Coprocessor Exception/Control Registers Memory Management Registers BrCond(3:0) Integer CPU Core General Registers (32 x 32) ALU Shifter Int(5:0) Translation Lookaside Buffer (64 entries) Mult/Div Unit Address Adder PC Control Virtual Address 32 Physical Address Bus Instruction Cache (8kB/4kB) Data Bus Bus Interface Unit 4-deep Write Buffer 4-deep Read Buffer DMA Arbiter Data Cache (2kB) 32 BIU Control Address/ Data DMA Ctrl Rd/Wr Ctrl SysClk 2874 drw 01 Figure 1. R3051 Family Block Diagram The IDT logo is a registered trademark, and RISChipset, RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400 and R4600 are trademarks of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE (c)1995 Integrated Device Technology, Inc. SEPTEMBER 1995 5.3 DSC-3000/5 1 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE INTRODUCTION The IDT IDT79R3051 family is a series of high-performance 32-bit microprocessors featuring a high level of integration which are targeted to high-performance, but costsensitive embedded processing applications. The IDT79R3051 family is designed to bring the high-performance inherent in the MIPS RISC architecture into low-cost, simplified, powersensitive applications. Functional units were integrated onto the CPU core in order to reduce the total system cost, without significantly degrading system performance. Thus, the IDT79R3051 family is able to offer 35MIPS of integer performance at 40MHz without requiring external SRAM or caches. Furthermore, the IDT79R3051 family brings dramatic power reduction to these embedded applications, allowing the use of low-cost packaging for devices up to 25 MHz. The IDT79R3051 family allows customer applications to bring maximum performance at minimum cost. Figure 1 shows a block-level representation of the functional units within the IDT79R3051 family. The IDT79R3051 family could be viewed as the embodiment of a discrete solution built around the IDT79R3000A or IDT79R3001. However, by integrating this functionality on a single chip, dramatic cost and power reductions are achieved. Currently, there are four members of the IDT79R3051 family. All devices are pin- and software-compatible: the differences lie in the amount of instruction cache, and in the memory management capabilities of the processor: * The IDT79R3052"E" incorporates 8kB of Instruction Cache, and features a full-function Memory Management Unit (MMU), including a 64-entry fully-associative Translation Lookaside Buffer (TLB). This is the same MMU incorporated into the IDT79R3000A and IDT79R3001. * The IDT79R3052 also incorporates 8kB of Instruction Cache. However, the MMU is a much simpler subset of the capabilities of the enhanced versions of the architecture, and in fact does not use a TLB. * The IDT79R3051"E" incorporates 4KB of Instruction Cache. Additionally, this device features the same full-function MMU (including TLB file) as the IDT79R3052"E", and IDT79R3000A. * The IDT79R3051 incorporates 4KB of Instruction Cache, and uses the simpler memory management model of the IDT79R3052. An overview of the functional blocks incorporated in these devices follows. CPU Core The CPU core is a full 32-bit RISC integer execution engine, capable of sustaining close-to single cycle execution rate. The CPU core contains a five stage pipeline and 32 orthogonal 32-bit registers. The IDT79R3051 family implements the MIPS ISA. In fact, the execution engine of the IDT79R3051 family is the same as the execution engine of the IDT79R3000A (and IDT79R3001). Thus the IDT79R3051 family is binary-compatible with those CPU engines. The execution engine of the IDT79R3051 family uses a five-stage pipeline to achieve close-to single cycle execution. A new instruction can be started in every clock cycle; the execution engine actually processes five instructions concurrently (in various pipeline stages). Figure 2 shows the concurrency achieved by the IDT79R3051 family pipeline. I#1 IF I#2 RD IF I#3 ALU MEM RD IF I#4 WB WB WB WB WB ALU MEM RD IF I#5 ALU MEM RD IF ALU MEM RD ALU MEM Current CPU Cycle Figure 2. R3051 Family 5-Stage Pipeline 2874 drw 02 System Control Co-Processor The R3051 family also integrates on-chip the System Control Co-processor, CP0. CP0 manages both the exception handling capability of the IDT79R3051 family, as well as the virtual to physical mapping of the IDT79R3051 family. There are two versions of the IDT79R3051 family architecture: the Extended Architecture Versions (the IDT79R3051E and IDT79R3052E) contain a fully associative 64-entry TLB which maps 4KB virtual pages into the physical address space. The virtual to physical mapping thus includes kernel segments which are hard mapped to physical addresses, and kernel and user segments which are mapped on a page basis by the TLB into anywhere within the 4GB physical address space. In this TLB, 8-page translations can be "locked" by the kernel to insure deterministic response in real-time applications. These versions thus use the same MMU structure as that found in the IDT79R3000A and IDT79R3001. Figure 3 shows the virtual-to-physical address mapping found in the Extended Architecture versions of the processor family. The Extended Architecture devices allow the system designer to implement kernel software to dynamically manage User task utilization of memory resources, and also allow the Kernel to effectively "protect" certain resources from user tasks. These capabilities are important in a number of embedded applications, from process control (where resource protection may be extremely important) to X-Window display systems (where virtual memory management is extremely important), and can also be used to simplify system debugging. 5.3 2 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE VIRTUAL 0xffffffff Kernel Mapped (kseg2) PHYSICAL Any 0xc0000000 Kernel Uncached (kseg1) 0xa0000000 Kernel Cached (kseg0) 0x80000000 Physical Memory 3548MB User Mapped Cacheable (kuseg) Any Memory 0x00000000 Figure 3. Virtual-to-Physical Mapping of Extended Architecture Versions 512MB 2874 drw 03 The base versions of the architecture (the IDT79R3051 and IDT79R3052) remove the TLB and institute a fixed address mapping for the various segments of the virtual address space. The base processors support distinct kernel and user mode operation without requiring page management software, leading to a simpler software model. The memory mapping used by these devices is illustrated in Figure 4. Note that the reserved address spaces shown are for compatibility with future family members; in the current family members, references to these addresses are translated in the same fashion as their respective segments, with no traps or exceptions taken. VIRTUAL 0xffffffff 1MB Kernel Rsvd When using the base versions of the architecture, the system designer can implement a distinction between the user tasks and the kernel tasks, without having to execute page management software. This distinction can take the form of physical memory protection, accomplished by address decoding, or in other forms. In systems which do not wish to implement memory protection, and wish to have the kernel and user tasks operate out of a single unified memory space, upper address lines can be ignored by the address decoder, and thus all references will be seen in the lower gigabyte of the physical address space. PHYSICAL Kernel Cached (kseg2) 0xc0000000 Kernel Uncached (kseg1) 0xa0000000 Kernel Cached (kseg0) 0x80000000 1MB User Rsvd User Cached (kuseg) 0x00000000 Kernel Cacheable Tasks 1024MB Kernel/User Cacheable Tasks 2048MB Inaccessible Kernel Boot and I/O 512MB 512MB 2874 drw 04 Figure 4. Virtual-to-Physical Mapping of Base Architecture Versions 5.3 3 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Clock Generation Unit The IDT79R3051 family is driven from a single input clock, capable of operating in a range of 40%-60% duty cycle. On chip, the clock generator unit is responsible for managing the interaction of the CPU core, caches, and bus interface. The clock generator unit replaces the external delay line required in IDT79R3000A and IDT79R3001 based applications. Instruction Cache The current family includes two different instruction cache sizes: the IDT79R3051 family (the IDT79R3051 and IDT79R3051E) feature 4KB of instruction cache, and the IDT79R3052 and IDT79R3052E each incorporate 8KB of Instruction Cache. For all four devices, the instruction cache is organized as a line size of 16 bytes (four words). This relatively large cache achieves a hit rate well in excess of 95% in most applications, and substantially contributes to the performance inherent in the IDT79R3051 family. The cache is implemented as a direct mapped cache, and is capable of caching instructions from anywhere within the 4GB physical address space. The cache is implemented using physical addresses (rather than virtual addresses), and thus does not require flushing on context switch. Data Cache All four devices incorporate an on-chip data cache of 2KB, organized as a line size of 4 bytes (one word). This relatively large data cache achieves hit rates well in excess of 90% in most applications, and contributes substantially to the performance inherent in the IDT79R3051 family. As with the instruction cache, the data cache is implemented as a direct mapped physical address cache. The cache is capable of mapping any word within the 4GB physical address space. The data cache is implemented as a write through cache, to insure that main memory is always consistent with the internal cache. In order to minimize processor stalls due to data write operations, the bus interface unit incorporates a 4deep write buffer which captures address and data at the processor execution rate, allowing it to be retired to main memory at a much slower rate without impacting system performance. Bus Interface Unit The IDT79R3051 family uses its large internal caches to provide the majority of the bandwidth requirements of the execution engine, and thus can utilize a simple bus interface connected to slow memory devices. The IDT79R3051 family bus interface utilizes a 32-bit address and data bus multiplexed onto a single set of pins. The bus interface unit also provides an ALE signal to demultiplex the A/D bus, and simple handshake signals to process processor read and write requests. In addition to the read and write interface, the IDT79R3051 family incorporates a DMA arbiter, to allow an external master to control the external bus. The IDT79R3051 family incorporates a 4-deep write buffer to decouple the speed of the execution engine from the speed of the memory system. The write buffers capture and FIFO processor address and data information in store operations, and presents it to the bus interface as write transactions at the rate the memory system can accommodate. The IDT79R3051/52 read interface performs both single word reads and quad word reads. Single word reads work with a simple handshake, and quad word reads can either utilize the simple handshake (in lower performance, simple systems) or utilize a tighter timing mode when the memory system can burst data at the processor clock rate. Thus, the system designer can choose to utilize page or nibble mode DRAMs (and possibly use interleaving), if desired, in high-performance systems, or use simpler techniques to reduce complexity. In order to accommodate slower quad-word reads, the IDT79R3051 family incorporates a 4-deep read buffer FIFO, so that the external interface can queue up data within the processor before releasing it to perform a burst fill of the internal caches. Depending on the cost vs. performance tradeoffs appropriate to a given application, the system design engineer could include true burst support from the DRAM to provide for high-performance cache miss processing, or utilize the read buffer to process quad word reads from slower memory systems. SYSTEM USAGE The IDT79R3051 family has been specifically designed to easily connect to low-cost memory systems. Typical low-cost memory systems utilize slow EPROMs, DRAMs, and application-specific peripherals. These systems may also typically contain large, slow Static RAMs, although the IDT79R3051 family has been designed to not specifically require the use of external SRAMs. Figure 5 shows a typical system block diagram. Transparent latches are used to de-multiplex the IDT79R3051/52 address and data busses from the A/D bus. The data paths between the memory system elements and the R3051 family A/D bus is managed by simple octal devices. A small set of simple PALs can be used to control the various data path elements, and to control the handshake between the memory devices and the CPU. DEVELOPMENT SUPPORT The IDT79R3051 family is supported by a rich set of development tools, ranging from system simulation tools through prom monitor support, logic analysis tools, and subsystem modules. Figure 7 is an overview of the system development process typically used when developing IDT79R3051 family-based applications. The IDT79R3051 family is supported by powerful tools through all phases of project development. These tools allow timely, parallel development of hardware and software for IDT79R3051/52 based applications, and include tools such as: * A program, Cache-3051, which allows the performance of an IDT79R3051 family based system to be modeled and understood without requiring actual hardware. 5.3 4 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE * Sable, an instruction set simulator. * Optimizing compilers from MIPS, the acknowledged leader in optimizing compiler technology. * IDT Cross development tools, available in a variety of development environments. * The high-performance IDT floating point library software, which has been integrated into the compiler toolchain to allow software floating point to replace hardware floating point without modifying the original source code. * The IDT Evaluation Board, which includes RAM, EPROM, I/O, and the IDT Prom Monitor. * The IDT Laser Printer System board, which directly drives a low-cost print engine, and runs Microsoft TrueImageTM Page Description Language on top of PeerlessPageTM Advanced Printer Controller BIOS. * Adobe PostScriptTM Page Description Language, ported to the R3000 instruction set, runs on the IDT79R3051 family. * The IDT Prom Monitor, which implements a full prom monitor (diagnostics, remote debug support, peek/poke, etc.). * An In-Circuit Emulator, developed and sold by Embedded Performance, Inc. Reset Clk2xIn Int(5:0) BrCond(3:0) IDT R3051 Family RISController BusReq BusGnt AD(31:0) ALE Addr(3:2) Wr SysClk Rd Burst/ RdCEn WrNear Ack DataEn BErr FCT373T Memory and Interface Control PALs Address Decode PAL DRAM Control PALs EPROM DRAM I/O Devices/ Peripherals System I/O FCT245T 2874 drw 05 Figure 5. Typical R3051 Family Based System 5.3 5 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Clk2xIn IDT79R3051 Family RISController Address/ Data Control R3051 Family Local Bus I/O Controller DRAM Controller PROM I/O I/O DRAM DRAM IDT73720 Bus Exchanger (2) 2874 drw 06 Figure 6. R3051 Family Chip Set Based System 5.3 6 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE System Architecture Evaluation System Development Phase System Integration and Verification Software SABLE Simulator DBG Debugger PIXIE Profiler MIPS Compiler Suite Stand-Alone Libraries Floating Point Library Cross Development Tools Adobe PostScriptTM PDL MicroSoft TrueImageTM PDL Ada Cache-R305x Benchmarks Evaluation Board Laser Printer System Logic Analysis Diagnostics IDT PROM Monitor Remote Debug Real-Time OS In-Circuit Emulator Hardware Cache-R305x Hardware Models General CAD Tools RISC Sub-systems Evaluation Board Laser Printer System 2874 drw 07 Figure 7. R3051 Family Development Toolchain 5.3 7 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE PERFORMANCE OVERVIEW The IDT79R3051 family achieves a very high level of performance. This performance is based on: * An efficient execution engine. The CPU performs ALU operations and store operations at a single cycle rate, and has an effective load time of 1.3 cycles, and a branch execution rate of 1.5 cycles (based on the ability of the compilers to avoid software interlocks). Thus, the execution engine achieves over 35MIPS performance when operating out of cache. * Large on-chip caches. The IDT79R3051 family contains caches which are substantially larger than those on the majority of today's embedded microprocessors. These large caches minimize the number of bus transactions required, and allow the R3051 family to achieve actual sustained performance, very close to its peak execution rate. * Autonomous multiply and divide operations. The IDT79R3051 family features an on-chip integer multiplier/ divide unit which is separate from the other ALU. This allows the IDT79R3051 family to perform multiply or divide operations in parallel with other integer operations, using a single multiply or divide instruction rather than "step" operations. * Integrated write buffer. The IDT79R3051 family features a four-deep write buffer, which captures store target addresses and data at the processor execution rate and retires it to main memory at the slower main memory access rate. Use of on-chip write buffers eliminates the need for the processor to stall when performing store operations. * Burst read support. The IDT79R3051 family enables the system designer to utilize page mode or nibble mode RAMs when performing read operations to minimize the main memory read penalty and increase the effective cache hit rates. These techniques combine to allow the processor to achieve 35MIPS integer performance, and over 64,000 dhrystones at 40MHz without the use of external caches or zero wait-state memory devices. THERMAL CONSIDERATIONS The IDT79R3051 family utilizes special packaging techniques to improve the thermal properties of high-speed processors. Thus, all versions of the IDT79R3051 family are packaged in cavity-down packaging. The lowest cost members of the family use a standard cavity-down, injection molded PLCC package (the "J" package). This package, coupled with the power reduction techniques employed in the design of the IDT79R3051 family, allows operation at speeds to 25MHz. However, at higher speeds, additional thermal care must be taken. For this reason, the IDT79R3051 family is also available in the MQUAD package (the "MJ" package), which is an allaluminum package with the die attached to a normal copper lead-frame, mounted to the aluminum casing. The MQUAD allows for more efficient thermal transfer between the die and the case of the part due to the heat-spreading effect of the aluminum. The aluminum offers less internal resistance from one end of the package to the other, which reduces the temperature gradient across the package, and, therefore, presents a greater area for convection and conduction to the PCB for a given temperature. Even nominal amounts of airflow will dramatically reduce the junction temperature of the die, resulting in cooler operation. The MQUAD package is available at all frequencies, and is pin- and form-compatible with the PLCC package. Thus, designers can choose to utilize this package without changing their PCB. The members of the IDT79R3051 family are guaranteed in a case temperature range of 0C to +85C. The type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient conditions which meet this specification. The equivalent allowable ambient temperature, TA, can be calculated using the thermal resistance from case to ambient (OCA) of the given package. The following equation relates ambient and case temperature: TA = TC - P * OCA where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device. Typical values for OCA at various airflows are shown in Table 1 for the various packages. Airflow (ft/min) OCA "J" Package "MJ" Package* 0 29 22 200 26 14 400 21 12 600 18 11 800 16 9 1000 15 8 2874 tbl 01 SELECTABLE FEATURES The IDT79R3051 family allows the system designer to configure some aspects of operation. These aspects are established when the device is reset and include: * Big Endian vs. Little Endian operation: The part can be configured to operate with either byte ordering convention, and in fact may also be dynamically switched between the two conventions. This facilitates the porting of applications from other processor architectures, and also permits intercommunications between various types of processors and databases. * Data cache refill of one or four words: The memory system must be capable of performing 4-word transfers to satisfy cache misses. This option allows the system designer to choose between one- and four-word refill on data cache misses, depending on the performance each option brings to his application. Table 1. Thermal Resistance (OCA) at Various Airflows (*estimated: final values tbd) 5.3 8 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION PIN NAME A/D(31:0) I/O I/O DESCRIPTION Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction in one phase, and which is used to transmit data between the CPU and external memory resources during the rest of the transfer. Bus transactions on this bus are logically separated into two phases: during the first phase, information about the transfer is presented to the memory system to be captured using the ALE output. This information consists of: Address(31:4): The high-order address for the transfer is presented on A/D(31:4). These strobes indicate which bytes of the 32-bit bus will be involved in the transfer, and are represented on A/D(3:0). BE BE(3:0): During write cycles, the bus contains the data to be stored and is driven from the internal write buffer. On read cycles, the bus receives the data from the external resource, in either a single data transaction or in a burst of four words, and places it into the on-chip read buffer. Addr(3:2) O Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor. Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes or single datum reads) or functions as a two bit counter starting at `00' for burst read operations. Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an onchip cache miss, and also presents part of the miss address. The value output on this pin is time multiplexed: Cached: During the phase in which the A/D bus presents address information, this pin is an active high output which indicates whether the current read is a result of a cache miss. The value of this pin at this time in other than read cycles is undefined. During the remainder of the read operation, this output presents address bit (3) of the address the processor was attempting to reference when the cache miss occurred. Regardless of whether a cache miss is being processed, this pin reports the transfer address during this time. Diag(1) O Miss Address (3): Diag(0) O Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from those due to data references, and presents the remaining bit of the miss address. The value output on this pin is also time multiplexed: I/D: D If the "Cached" Pin indicates a cache miss, then a high on this pin at this time indicates an instruction reference, and a low indicates a data reference. If the read is not due to a cache miss but rather an uncached reference, then this pin is undefined during this phase. During the remainder of the read operation, this output presents address bit (2) of the address the processor was attempting to reference when the cache miss occurred. Regardless of whether a cache miss is being processed, this pin reports the transfer address during this time. Miss Address (2): ALE O Address Latch Enable: Used to indicate that the A/D bus contains valid address information for the bus transaction. This signal is used by external logic to capture the address for the transfer, typically using transparent latches. External Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor during read cycles, and thus the external memory system may enable the drivers of the memory system onto this bus without having a bus conflict occur. During write cycles, or when no bus transaction is occurring, this signal is negated, thus disabling the external memory drivers. 2874 tbl 02 DataEn O 5.3 9 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (Continued): PIN NAME I/O O DESCRIPTION Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles due to cache misses; it is asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles if selected at device reset time. On write transactions, the WrNear output tells the external memory system that the bus interface unit is performing back-to-back write transactions to an address within the same 256 word page as the prior write transaction. This signal is useful in memory systems which employ page mode or static column DRAMs, and allows near writes to be retired quickly. Burst/ WrNear Rd Wr Ack RdCEn SysClk BusReq BusGnt SBrCond(3:2) BrCond(1:0) O O I Read: An output which indicates that the current bus transaction is a read. Write: An output which indicates that the current bus transaction is a write. Acknowledge: An input which indicates to the device that the memory system has sufficiently processed the bus transaction, and that the CPU may either terminate the write cycle or process the read data from this read transfer. Read Buffer Clock Enable: An input which indicates to the device that the memory system has placed valid data on the A/D bus, and that the processor may move the data into the on-chip Read Buffer. System Reference Clock: An output from the CPU which reflects the timing of the internal processor "Sys" clock. This clock is used to control state transitions in the read buffer, write buffer, memory controller, and bus interface unit. DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus interface signals so that they may be driven by an external master. DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been detected, and that the bus is relinquished to the external master. Branch Condition Port: These external signals are internally connected to the CPU signals CpCond(3:0). These signals can be used by the branch on co-processor condition instructions as input ports. There are two types of Branch Condition inputs: the SBrCond inputs have special internal logic to synchronize the inputs, and thus may be driven by asynchronous agents. The direct Branch Condition inputs must be driven synchronously. Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error. This signal is only sampled during read and write operations. If the bus transaction is a read operation, then the CPU will take a bus error exception. Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0) signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but in a different (simpler) fashion than the interrupt signals of the R3000. There are two types of interrupt inputs: the SInt inputs are internally synchronized by the processor, and may be driven by an asynchronous external agent. The direct interrupt inputs are not internally synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have one cycle lower latency than the synchronized interrupts. I O I O I BErr Int(5:3) SInt(2:0) I I Clk2xIn I I I/O Master Clock Input: This is a double frequency input used to control the timing of the CPU. Master Processor Reset: This signal initializes the CPU. Mode selection is performed during the last cycle of Reset. Reserved: These five signal pins are reserved for testing and for future revisions of this device. Users must not connect these pins. 2874 tbl 03 Reset Rsvd(4:0) 5.3 10 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1, 3) Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Case Temperature Temperature Under Bias Storage Temperature Input Voltage Commercial -0.5 to +7.0 Unit V RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Commercial Temperature 0C to +85C (Case) GND 0V VCC 5.0 5% 2874 tbl 06 TC TBIAS TSTG VIN 0 to +85 -55 to +125 -55 to +125 -0.5 to +7.0 C C C V OUTPUT LOADING FOR AC TESTING +4mA NOTES: 2874 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VIN minimum = -3.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5V. 3. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. VREF +1.5V - + To Device Under Test 25pF -4mA 2874 drw 08 AC TEST CONDITIONS Symbol VIH VIL VIHS VILS Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Input LOW Voltage Min. 3.0 -- 3.5 -- Max. -- 0 -- 0 Unit V V V V 2874 tbl 05 DC ELECTRICAL CHARACTERISTICS (TC = 0C to +85C, VCC = +5.0V 5%) 20MHz Symbol VOH VOL VIH VIL VIHS VILS CIN COUT ICC IIH IIL IOZ Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Input HIGH Input LOW Input Voltage(3) Voltage(1) Voltage(2,3) Voltage(1,2) Test Conditions VCC = Min., IOH = -4mA VCC = Min., IOL = 4mA -- -- -- -- -- -- VCC = 5V, TC = 25C VIH = VCC VIL = GND VOH = 2.4V, VOL = 0.5V Min. 3.5 -- 2.0 -- 3.0 -- -- -- -- -- -100 -100 Max. -- 0.4 -- 0.8 -- 0.4 10 10 350 100 -- 100 25MHz Min. 3.5 -- 2.0 -- 3.0 -- -- -- -- -- -100 -100 Max. -- 0.4 -- 0.8 -- 0.4 10 10 400 100 -- 100 33.33MHz Min. 3.5 -- 2.0 -- 3.0 -- -- -- -- -- -100 -100 Max. -- 0.4 -- 0.8 -- 0.4 10 10 450 100 -- 100 40MHz Min. 3.5 -- 2.0 -- 3.0 -- -- -- -- -- -100 -100 Max. Unit -- 0.4 -- 0.8 -- 0.4 10 10 500 100 -- 100 V V V V V V pF pF mA A A A 2874 tbl 07 Capacitance(4) Capacitance(4) Output Operating Current Input HIGH Leakage Input LOW Leakage Output Tri-state Leakage NOTES: 1. VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -0.5V for larger periods. 2. VIHS and VILS apply to CIk2xIn and Reset. 3. VIH should not be held above VCC + 0.5V. 4. Guaranteed by design. 5.3 11 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS Symbol t1 t1a t2 Signals (1, 2, 3) (TC = 0C to +85C, VCC = +5.0V 5%) 20MHz 25MHz Min. 5 6 4 Max. -- -- -- 33.33MHz Min. 4 5 3 Max. -- -- -- 40MHz Min. 3 4.5 3 Max. -- -- -- Unit ns ns ns Min. 6 7 4 Max. -- -- -- Description Set-up to SysClk rising Set-up to SysClk falling Hold from SysClk rising Hold from SysClk falling Tri-state from SysClk rising Driven from SysClk falling Asserted from SysClk rising Valid from SysClk rising BusReq, Ack, BusError, RdCEn, A/D BusReq, Ack, BusError, RdCEn, A/D A/D, Addr, Diag, ALE, Wr Burst/WrNear, Rd, DataEn A/D, Addr, Diag, ALE, Wr Burst/WrNear, Rd, DataEn BusGnt BusGnt Wr, Rd, Burst/WrNear, A/D ALE ALE A/D t2a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 tsys t32 t33 tderate 2 -- -- -- -- -- -- -- 2 -- 0 0 -- -- -- -- -- 10 10 25 200 32 6 6 2.5 6 3 6 3 2*t22 -- 10 10 8 8 5 4 4 -- 15 -- -- 7 6 12 10 12 -- -- 250 -- -- -- -- -- -- -- -- -- 2*t22 2 -- -- -- -- -- -- -- 2 -- 0 0 -- -- -- -- -- 8 8 20 200 32 5 5 2.5 5 3 5 3 2*t22 -- 10 10 7 7 5 4 4 -- 15 -- -- 6 6 11 10 11 -- -- 250 -- -- -- -- -- -- -- -- -- 2*t22 1 -- -- -- -- -- -- -- 1.5 -- 0 0 -- -- -- -- -- 6.5 6.5 15 200 32 4 4 2.5 4 2 4 2 2*t22 -- 10 10 6 6 4 3 3 -- 13 -- -- 5 5 10 9 10 -- -- 250 -- -- -- -- -- -- -- -- -- 2*t22 1 -- -- -- -- -- -- -- 1.5 -- 0 0 -- -- -- -- -- 5.6 5.6 12.5 200 32 3 3 2.5 3 2 3 2 2*t22 -- 10 10 5 5 3.5 3 3 -- 12 -- -- 4 4.5 9 8 9 -- -- 250 -- -- -- -- -- -- -- -- -- 2*t22 ns ns ns/ 25pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s tsys ns ns ns ns ns ns ns Negated from SysClk falling Asserted from SysClk rising Negated from SysClk falling Hold from ALE negated Asserted from SysClk falling Asserted from A/D tri-state(4) Driven from SysClk rising(4) Valid from SysClk Valid from SysClk DataEn DataEn A/D Wr, Rd, DataEn, Burst/WrNear Addr(3:2) Diag A/D A/D Clk2xIn Clk2xIn Clk2xIn Negated from SysClk falling Tri-state from SysClk falling SysClk falling to data out Pulse Width HIGH Pulse Width LOW Clock Period Pulse Width from Vcc valid Minimum Pulse Width Set-up to SysClk falling Mode set-up to Reset rising Set-up to SysClk falling Set-up to SysClk falling Pulse Width Clock HIGH Time Clock LOW Time Timing deration for loading over 25pf(4, 5) Reset Reset Reset Int Int SInt, SBrCond SInt, SBrCond Int, BrCond Int, BrCond SysClk SysClk SysClk All outputs Mode hold from Reset rising Hold from SysClk falling Hold from SysClk falling t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 1 t22 + 1 t22 - 1 t22 + 1 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 1 t22 + 1 t22 - 1 t22 + 1 -- 0.5 -- 0.5 -- 0.5 -- 0.5 NOTES: 2874 tbl 08 1. All timings referenced to 1.5V, with a rise and fall time of less than 2.5ns. 2. All outputs tested with 25pF loading. 3. The AC values listed here reference timing diagrams contained in the R3051 Family Hardware User's Manual. 4. Guaranteed by design. 5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified test condition; that is, the deration factor is applied for each 25pF over the specified test load condition. 5.3 12 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS A/D(31) A/D(30) A/D(29) A/D(28) A/D(27) A/D(26) A/D(25) A/D(24) A/D(23) A/D(22) A/D(21) A/D(20) A/D(19) A/D(18) A/D(17) A/D(16) VCC VCC VSS VSS A/D(15) 1 VSS VCC Clk2xIn Rsvd(4) Rsvd(3) Rsvd(2) Rsvd(1) Rsvd(0) 12 84 75 VSS VCC A/D(14) A/D(13) A/D(12) A/D(11) A/D(10) A/D(9) VCC VSS A/D(8) A/D(7) A/D(6) A/D(5) A/D(4) A/D(3) VSS VCC A/D(2) A/D(1) 54 A/D(0) Int(5) VSS VCC Int(4) Int(3) SInt(2) SInt(1) SInt(0) SBrCond(3) SBrCond(2) BrCond(1) VSS VCC 33 BusReq RdCEn ACK VSS BusError BusGnt SysClk DataEn Wr Rd VSS Burst/WrNear BrCond(0) Addr(2) Addr(3) Diag(0) Diag(1) Reset ALE VCC VCC 2874 drw 09 84-Pin PLCC/MQUAD Top View NOTE: Reserved Pins must not be connected. 5.3 13 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE t22 Clk2xIn t20 t21 SysClk t32 t33 tsys 2874 drw 11 Figure 8. R3051 Family Clocking VCC ClkIn Reset t23 2874 drw 12 Figure 9. Power-On Reset Sequence SysClk Reset t24 2874 drw 13 Figure 10. Warm Reset Sequence SysClk Reset SInt(n), Int(n) t26 t27 Figure 11. Mode Selection and Negation of Reset 2874 drw 14 t25 5.3 14 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Run/ Fixup/ Stall PhiClk Stall Stall Stall Stall Stall Fixup SysClk t7 t15 Rd t14 A/D(31:0) t16 Addr(3:2) t8 ALE t9 t12 t15 Addr BE t18 t1a Data Input t14 t10 Word Address t2a DataEn t7 t11 Burst t1 RdCEn t2 ACK t17 Diag(1) t17 Cached? Miss Address(3) Diag(0) I/D Miss Address(2) Start Read Turn Bus ACK? ACK? ACK/ RdCen Sample Data End Read 2874 drw 15 Figure 12. Single Datum Read in R3051 Family 5.3 15 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Run/ Fixup/ Stall PhiClk Stall Stall Stall Refill/ Stream/ Fixup Word 0 Refill/ Stream/ Fixup Word 1 Refill/ Stream/ Fixup Word 2 Refill/ Stream/ Fixup Word 3 SysClk t7 t15 t18 Addr BE Rd t14 A/D(31:0) t16 Addr(3:2) t8 ALE t12 t15 t1a Word 0 t1a Word 1 t1a Word 2 t1a Word 3 t14 t10 '00' t2a '01' t2a '10' t2a '11' t2a t9 t16 t16 t16 DataEn t7 t11 Burst t1 t1 t2 t1 t2 t1 t2 RdCEn t2 ACK t17 Diag(1) t17 Cached? Miss Address(3) Diag(0) Start Read I/D Miss Address(2) Turn Bus ACK/ Sample RdCEn Sample RdCEn Sample RdCEn Sample New Data Data Data Transaction RdCen Data 2874 drw 16 Figure 13. R3051 Family Burst Read 5.3 16 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Stall Stall Stall Stall PhiClk SysClk Rd t1a A/D(31:0) Word 0 t1a Word 1 t2a Addr(3:2) '00' '01' t2a '10' t16 ALE t16 DataEn Burst t1 t1 t2 t1 t2 RdCEn t2 ACK RdCEn Sample Data RdCEn Sample Data RdCEn Sample Data 2874 drw 17 Figure 14 (a). Start of Throttled Quad Read 5.3 17 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Stall Refill/ Stream/ Fixup Word 0 Refill/ Stream/ Fixup Word 1 Refill/ Stream/ Fixup Word 2 Refill/ Stream/ Fixup Word 3 PhiClk SysClk Rd t1a A/D(31:0) Word 2 t15 t1a Word 3 t14 t2a Addr(3:2) '01' '11' t2a t16 ALE t15 DataEn Burst t1 t1 t2 t1 t2 RdCEn t1 t2 ACK t2 ACK RdCEn Sample Data RdCEn Sample Data New Transaction 2874 drw 18 Figure 14 (b). End of Throttled Quad Read 5.3 18 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE SysClk t7 t15 t19 Addr BE Data Out Wr t14 A/D(31:0) t16 Addr(3:2) t8 ALE t7 t9 t15 t10 Word Address t14 WrNear t2 ACK Start Write Data Out ACK ACK t1 ACK Negate Wr New Transfer 2874 drw 19 Figure 15. R3051 Family Write Cycle SysClk BusReq t1 t2 t5 t3 BusGnt A/D(31:0) Addr(3:2) Diag(1:0) Rd Wr ALE Burst/ WrNear Figure 16. Request and Relinquish of R3051 Family Bus to External Master 2874 drw 20 5.3 19 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE SysClk BusReq BusGnt A/D(31:0) t2 t1 t6 t4 Addr(3:2) Diag(1:0) Rd Wr ALE Burst/ WrNear 2874 drw 21 Figure 17. R3051 Family Regaining Bus Mastership 5.3 20 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Run Cycle Phi Exception Vector SysClk SInt(n) t 28 t 29 2874 drw 22 Figure 18. Synchronized Interrupt Input Timing Run Cycle Phi Exception Vector SysClk Int(n) 2874 drw 23 t30 t31 Figure 19. Direct Interrupt Input Timing Run Cycle Phi Capture BrCond BCzT/F Instruction SysClk SBrCond(n) t28 t29 2874 drw 24 Figure 20. Synchronized Branch Condition Input Timing Run Cycle Phi Capture BrCond BCzT/F Instruction SysClk BrCond(n) t30 t31 2874 drw 25 Figure 21. Direct Branch Condition Input Timing 5.3 21 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE 84 LEAD PLCC/MQUAD(7) (SQUARE) A D D1 45 x .045 A1 PIN 1 C D3/E3 E1 E b1 B D2/E2 e C1 NOTES: 1. All dimensions are in inches, unless otherwise noted. 2. BSC--Basic lead Spacing between Centers. 3. D & E do not include mold flash or protutions. 4. Formed leads shall be planar with respect to one another and within .004" at the seating plane. 5. ND & NE represent the number of leads in the D & E directions respectively. 6. D1 & E1 should be measured from the bottom of the package. 7. MQUAD is pin & form compatible with PLCC. SEATING PLANE 2874 drw 27 DWG # # of Leads Symbol A A1 B b1 C C1 D D1 D2/E2 D3/E3 E E1 e ND/NE Min. 165 .095 .026 .013 .020 .008 1.185 1.150 1.090 J84-1 84 Max. .180 .115 .032 .021 .040 .012 1.195 1.156 1.130 MJ84-1 84 Min. 165 .094 .026 .013 .020 .008 1.185 1.140 1.090 Max. .180 .114 .032 .021 .040 .012 1.195 1.150 1.130 1.000 REF 1.185 1.150 1.195 1.156 1.000 REF 1.185 1.140 1.195 1.150 .050 BSC 21 .050 BSC 21 5.3 22 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION XXXXX IDT Device Type Speed Package Process/ Temp. Range XX X X Blank Commercial Temperature Range 'J' 'MJ' 84-Pin PLCC 84-Pin MQUAD '20' '25' '33' '40' 79R3051 79R3051E 79R3052 79R3052E 20.0 MHz 25.0 MHz 33.33 MHz 40.0 MHz 4kB Instruction Cache, No TLB 4kB Instruction Cache, With TLB 8kB Instruction Cache, No TLB 8kB Instruction Cache, With TLB 2874 drw 28 VALID COMBINATIONS IDT 79R3051 - 20, 25 79R3051E - 20, 25 79R3052 - 20, 25 79R3052E - 20, 25 79R3051 - 33, 40 79R3051E - 33, 40 79R3052 - 33, 40 79R3052E - 33, 40 J Packages Only J Packages Only J Packages Only J Packages Only MJ Packages Only MJ Packages Only MJ Packages Only MJ Packages Only 5.3 23 |
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